Reload Register (Iwdg_Rlr); Status Register (Iwdg_Sr) - ST STM32F100 Series Reference Manual

Independent watchdog (IWDG)
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
18.4.3

Reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
Note: Reading this register returns the reload value from the VDD voltage domain. This value
18.4.4

Status register (IWDG_SR)

Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
484/709
These bits are write access protected
select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
Reserved
These bits are write access protected see
define the value to be loaded in the watchdog counter each time the value AAAAh is written
in the IWDG_KR register. The watchdog counter counts down from this value. The timeout
period is a function of this value and the clock prescaler. Refer to
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.
seeSection
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Section
Reserved
RM0041 Rev 6
18.3.2. They are written by software to
9 8 7 6 5
RL[11:0]
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18.3.2. They are written by software to
Table 86.
9 8 7 6 5 4
RM0041
4 3 2 1 0
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3 2 1 0
RVU PVU
r r