Figure 248. Data Sampling When Oversampling By 16 - ST STM32F100 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
•
the majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
• a single sample in the center of the received bit
Depending on the application:
–
–
When noise is detected in a frame:
•
The NF bit is set at the rising edge of the RXNE bit.
•
The invalid data is transferred from the Shift register to the USART_DR register.
•
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt is issued if the EIE bit is set in the USART_CR3
register.
The NF bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes,
the OVER8 bit is forced to '0 by hardware.
RX line
Sample clock
610/709
select the three samples' majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 124) because this indicates that a glitch occurred during the sampling.
select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver's tolerance to clock deviations (see
receiver tolerance to clock deviation on page
set.

Figure 248. Data sampling when oversampling by 16

1 2 3
sampled values
4 5 6 7 8 9
7/16
One bit time
RM0041 Rev 6
Section 23.3.5: USART
617). In this case the NF bit is never
10 11 12 13 14 15
6/16
7/16
RM0041
16
MSv31152V1