Figure 163. Counter Timing Diagram, Internal Clock Divided By 4; Figure 164. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F100 Series Reference Manual

General-purpose timers (TIM15/16/17)
Figure 165. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
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Figure 163. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 164. Counter timing diagram, internal clock divided by N

CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
RM0041 Rev 6
0035
1F
20
preloaded)
CEN
31 32 33 34 35 36
FF
0036 0000 0001
00
00 01 02 03 04 05 06 07
36
RM0041