Figure 189. Counter Timing Diagram, Internal Clock Divided By 1; Figure 190. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F100 Series Reference Manual

Basic timers (TIM6 and TIM7)
Timerclock = CK_CNT
Update interrupt flag (UIF)
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Figure 189. Counter timing diagram, internal clock divided by 1

CK_INT
CNT_EN
Counter register 31
Counter overflow
Update event (UEV)

Figure 190. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
32 33 34 35 36
0034 0035 0036
RM0041 Rev 6
00 01 02 03 04 05
0000 0001 0002
RM0041
06 07
MS37364V1
0003
MS35835V1