External Interrupt Configuration Register 1 (Afio_Exticr1); External Interrupt Configuration Register 2 (Afio_Exticr2) - ST STM32F100 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.4.3

External interrupt configuration register 1 (AFIO_EXTICR1)

Address offset: 0x08
Reset value: 0x0000
31 30 29
15 14 13
EXTI3[3:0]
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Bits 31:16
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
7.4.4

External interrupt configuration register 2 (AFIO_EXTICR2)

Address offset: 0x0C
Reset value: 0x0000
31 30 29
15 14 13
EXTI7[3:0]
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Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
126/709
28 27 26 25
12 11 10 9
EXTI2[3:0]
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Reserved
These bits are written by software to select the source input for EXTIx external interrupt.
Refer to Section 8.2.5: External interrupt/event line mapping
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
28 27 26 25
12 11 10 9
EXTI6[3:0]
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24 23 22
Reserved
8 7 6
EXTI1[3:0]
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24 23 22
Reserved
8 7 6
EXTI5[3:0]
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RM0041 Rev 6
21 20 19 18
5 4 3 2
EXTI0[3:0]
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21 20 19 18
5 4 3 2
EXTI4[3:0]
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RM0041
17 16
1 0
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17 16
1 0
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