Figure 187. Counter Timing Diagram With Prescaler Division Change From 1 To 2 - ST STM32F100 Series Reference Manual

Basic timers (TIM6 and TIM7)
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 187
ratio is changed on the fly.

Figure 187. Counter timing diagram with prescaler division change from 1 to 2

Timerclock = CK_CNT
Update event (UEV)
Prescaler control register
Prescaler counter
458/709
and Figure 188 give some examples of the counter behavior when the prescaler
CK_PSC
CNT_EN
Counter register F7
Write a new value in TIMx_PSC
Prescaler buffer
F8 F9 FA FB FC
0
0
0
RM0041 Rev 6
00 01 02
1
1
0 1 0 1
1 0
RM0041
03
1
0
MS31076V3