General Timing Rules; Nor Flash/Psram Controller Asynchronous Transactions - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)
Table 97. NOR flash/PSRAM controller: example of supported memories and transactions
Device
Asynchronous
Asynchronous
SRAM and ROM
Asynchronous
Asynchronous
20.5.3

General timing rules

Signals synchronization
•
All controller output signals change on the rising edge of the internal clock (HCLK)
•
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
20.5.4

NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash memory, PSRAM, SRAM)
•
Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
•
The FSMC always samples the data before de-asserting the NOE signals. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
•
If the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up
to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and
D modes for read and write operations. For example, read operation can be performed
in mode A and write in mode B.
•
If the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register),
the FSMC can operate in Mode1 or Mode2 as follows:
–
–
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers.
502/709
Mode R/W
R
W
R
W
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
Mode 1 is the default mode when SRAM/PSRAM memory type is selected
(MTYP[0:1] = 0x0 or 0x01 in the FSMC_BCRx register)
Mode 2 is the default mode when NOR memory type is selected (MTYP[0:1] =
0x10 in the FSMC_BCRx register).
AHB Allowed/
Memory
data
data size
size allowed
8 / 16 16
8 / 16 16
32 16
32 16
RM0041 Rev 6
not Comments
Y -
Y Use of byte lanes NBL[1:0]
Y Split into two FSMC accesses
Split into two FSMC accesses.
Y
Use of byte lanes NBL[1:0]
RM0041