Tim16&Tim17 Status Register (Timx_Sr) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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TIM16&TIM17 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF: Capture/Compare 1 overcapture flag

Bit 8 Reserved, must be kept at reset value.

Bit 7 BIF: Break interrupt flag

Bit 6 TIF: Trigger interrupt flag

Bit 5 COMIF: COM interrupt flag

This flag is set by hardware only when the corresponding channel is configured in input

capture mode. It is cleared by software by writing it to '0'.

0: No overcapture has been detected

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was

This flag is set by hardware as soon as the break input goes active. It can be cleared by

software if the break input is not active.

0: No break event occurred

1: An active level has been detected on the break input

This flag is set by hardware on trigger event (active edge detected on TRGI input when the

slave mode controller is enabled in all modes but gated mode, both edges in case gated

mode is selected). It is cleared by software.

0: No trigger event occurred

1: Trigger interrupt pending

This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,

CCxNE, OCxM– have been updated). It is cleared by software.

0: No COM event occurred

1: COM interrupt pending

General-purpose timers (TIM15/16/17)

RM0041 Rev 6

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