Figure 51. Counter Timing Diagram, Internal Clock Divided By 4; Figure 52. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F100 Series Reference Manual

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
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Figure 51. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 52. Counter timing diagram, internal clock divided by N

CK_PSC
20
(UIF)
RM0041 Rev 6
0001 0000
1F 00
RM0041
0036 0035
MS40510V1
36
MS31187V1