ST STM32F100 Series Reference Manual page 262

Advanced-control timer (TIM1)
Bits 11:8 ETF[3:0]: External trigger filter
Bit 7 MSM: Master/slave mode
Bits 6:4 TS[2:0]: Trigger selection
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
Bit 3 Reserved, must be kept at reset value.
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This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
0001: f =f
SAMPLING CK_INT
0010: f =f
SAMPLING CK_INT
0011: f =f
SAMPLING CK_INT
0100: f =f /2, N=6
SAMPLING DTS
0101: f =f /2, N=8
SAMPLING DTS
0110: f =f /4, N=6
SAMPLING DTS
0111: f =f /4, N=8
SAMPLING DTS
1000: f =f /8, N=6
SAMPLING DTS
1001: f =f /8, N=8
SAMPLING DTS
1010: f =f /16, N=5
SAMPLING DTS
1011: f =f /16, N=6
SAMPLING DTS
1100: f =f /16, N=8
SAMPLING DTS
1101: f =f /32, N=5
SAMPLING DTS
1110: f =f /32, N=6
SAMPLING DTS
1111: f =f /32, N=8
SAMPLING DTS
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 67 for more details on ITRx meaning for each Timer.
avoid wrong edge detections at the transition.
DTS
, N=2
, N=4
, N=8
RM0041 Rev 6
RM0041