Figure 172. Capture/Compare Channel 1 Main Circuit; Figure 173. Output Stage Of Capture/Compare Channel (Channel 1); Figure 174. Output Stage Of Capture/Compare Channel (Channel 2 For Tim15) - ST STM32F100 Series Reference Manual

RM0041
read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_EGR
CNT>CCR1
CNT=CCR1

Figure 174. Output stage of capture/compare channel (channel 2 for TIM15)

CNT > CCR2
CNT = CCR2

Figure 172. Capture/compare channel 1 main circuit

S
read_in_progress
Capture/compare preload register
R
capture_transfer
input
mode
Capture/compare shadow register

Figure 173. Output stage of capture/compare channel (channel 1)

Output mode OC1REF
controller
OC1CE OC1M[2:0]
TIMx_CCMR1
OC2_REF
Output mode
controller
OC2M[2:0]
TIM15_CCMR2
General-purpose timers (TIM15/16/17)
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
'0'
x0
01
OC1_DT
11
Dead-time
generator
OC1N_DT
11
10
'0'
0x
DTG[7:0] CC1NE CC1E
TIMx_BDTR TIMx_CCER
To the master mode
controller
RM0041 Rev 6
write CCR1H
S
write_in_progress
write CCR1L
R
CC1S[1]
output
mode
CC1S[0]
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
0
Output
enable
circuit
1
CC1P
TIMx_CCER
0
Output
enable
circuit
1
CC1NE CC1E TIMx_CCER
CC1NP MOE OSSI OSSR
TIMx_CCER
0
Output
enable
circuit
1
CC2P
TIM15_CCER
CC2E TIM15_CCER
MOE OSSI TIM15_BDTR
OIS2
OC1PE
OC1PE
TIM1_CCMR1
OC1
OC1N
TIMx_BDTR
ai17333b
OC2
TIM15_CR2
ai17334
401/709
455