Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll) - ST STM32F100 Series Reference Manual

Real-time clock (RTC)
The functions of the RTC are controlled by this control register. It is not possible to write to
the RTC_CR register while the peripheral is completing a previous write operation (flagged
by RTOFF=0, see
Note: Any flag remains pending until the appropriate RTC_CR request bit is reset by software,
indicating that the interrupt request has been granted.
At reset the interrupts are disabled, no interrupt requests are pending and it is possible to
write to the RTC registers.
The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running.
The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by
software.
If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also
enabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm
interrupt are enabled.
If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI
Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is
generated on this line (no RTC Alarm interrupt generation).
17.4.3

RTC prescaler load register (RTC_PRLH / RTC_PRLL)

The Prescaler Load registers keep the period counting value of the RTC prescaler. They are
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if
the RTOFF value is '1'.
RTC prescaler load register high (RTC_PRLH)
Address offset: 0x08
Write only (see
Reset value: 0x0000
15 14 13
Bits 15:4 Reserved, forced by hardware to 0.
Bits 3:0 PRL[19:16]: RTC prescaler reload value high
These bits are used to define the counter clock frequency according to the following formula:
f
TR_CLK
476/709
Section 17.3.4: Configuring RTC
Section 17.3.4: Configuring RTC
12 11 10 9
Reserved
= f /(PRL[19:0]+1)
RTCCLK
registers).
registers)
8 7 6
RM0041 Rev 6
5 4 3 2
PRL[19:16]
w w
RM0041
1 0
w w