ST STM32F100 Series Reference Manual page 609

RM0041
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
•
The ORE bit is set.
•
The RDR content is not lost. The previous data is available when a read to USART_DR
is performed.
•
The shift register is overwritten. After that point, any data received during overrun is
lost.
•
An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
•
The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
•
if RXNE=1, then the last valid data is stored in the receive register RDR and can be
read,
•
if RXNE=0, then it means that the last valid data has already been read and thus there
is nothing to be read in the RDR. This case can occur when the last valid data is read in
the RDR at the same time as the new (and lost) data is received. It may also occur
when the new data is received during the reading sequence (between the USART_SR
register read access and the USART_DR read access).
Selecting the proper oversampling method
The receiver implements different user-configurable oversampling techniques (except in
synchronous mode) for data recovery by discriminating between valid incoming data and
noise.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock
Figure 249).
Depending on the application:
•
select oversampling by 8 (OVER8=1) to achieve higher speed (up to f
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 23.3.5: USART receiver tolerance to clock deviation on page
•
select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock
deviations. In this case, the maximum speed is limited to maximum f
Universal synchronous asynchronous receiver transmitter (USART)
RM0041 Rev 6
(Figure 248 and
/8). In this
PCLK
617)
/16
PCLK
609/709
646