Table 148. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2] - ST STM32F100 Series Reference Manual

RM0041
IR(3:0)
1011
1000

Table 148. 32-bit debug port registers addressed through the shifted value A[3:2]

Address A[3:2] value
0x0
0x4
0x8
0xC
Table 147. JTAG debug port data registers (continued)
Data register
Access port access register
Initiates an access port and allows access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Bit 0 = RnW= Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
APACC
request
[35 bits]
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
There are many AP registers (see AHB-AP) addressed as the
combination of:
– The shifted value A[3:2]
– The current value of the DP SELECT register
Abort register
ABORT
– Bits 31:1 = Reserved
[35 bits]
– Bit 0 = DAPABORT: write 1 to generate a DAP abort.
00 Reserved, must be kept at reset value.
DP CTRL/STAT register. Used to:
– Request a system or debug power-up
01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
11 after a sequence of operations (without requesting new JTAG-DP
operation)
Description
RM0041 Rev 6
Debug support (DBG)
Details
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