ST STM32F100 Series Reference Manual page 597

RM0041 Inter-integrated circuit (I2C) interface
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
These bits should provide the maximum duration of the SCL feedback loop in master mode.
The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
2
These bits must be programmed with the maximum SCL rise time given in the I C bus
specification, incremented by 1.
For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T = 125 ns
PCLK1
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t parameter.
HIGH
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
RM0041 Rev 6 597/709
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