Table 5. Flash Module Organization (High-Density Value Line Devices) - ST STM32F100 Series Reference Manual

Memory and bus architecture
Table 5. Flash module organization (high-density value line devices) (continued)
Block
Flash memory
interface
registers
Note: For further information on the flash memory interface registers, refer to PM0063.
Reading flash memory
Flash memory accesses are performed through the AHB bus. Accesses are either
instruction fetches over the ICode bus, or data accesses (e.g. literal pool) over the D-code
bus. Since these two buses have the same flash memory as target, the interface gives
priority to D-code bus accesses over I-code bus, instruction fetch accesses.
Read accesses can be performed without any wait state and with the following configuration
options:
•
Half cycle: for power optimization
Note: 1 Half cycle configuration is not available in combination with a prescaler on the AHB. The
system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.
2 Using DMA: DMA accesses flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing flash memory
The flash memory can be programmed 16 bits (half words) at a time. For write and erase
operations on the flash memory (write/erase), the internal RC oscillator (HSI) must be ON.
The flash memory erase operation can be performed at page level or on the whole area
(mass erase). Mass erase does not affect the information blocks.
To ensure that there is no overprogramming, the flash programming and erase controller
blocks are clocked by a fixed clock.
The end of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit the WFI mode, only if the FLASH clock is enabled. Otherwise, the
interrupt is served only after exiting WFI.
The FLASH_ACR register is used to enable/disable flash memory half-cycle access. The
tables below provide the bit map and bit descriptions for this register.
44/709
Name
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
RM0041 Rev 6
Base addresses
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
RM0041
Size (bytes)
4
4
4
4
4
4
4
4
4