Table 95. Nonmultiplexed I/Os Psram/Sram; Table 96. Multiplexed I/O Psram - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)
FSMC signal name
NL(=NADV)
NWAIT
NOR-flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
PSRAM/SRAM, nonmultiplexed I/Os
FSMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
PSRAM, multiplexed I/Os
FSMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
500/709
Table 94. Multiplexed I/O NOR flash (continued)
I/O
Latch enable (this signal is called address valid, NADV, by some NOR
O
flash devices)
I NOR flash wait input signal to the FSMC

Table 95. Nonmultiplexed I/Os PSRAM/SRAM

I/O
O Clock (only for PSRAM synchronous access)
O Address bus
I/O Data bidirectional bus
O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O Output enable
O Write enable
O Address valid only for PSRAM input (memory signal name: NADV)
I PSRAM wait input signal to the FSMC
O Upper byte enable (memory signal name: NUB)
O Lowed byte enable (memory signal name: NLB)

Table 96. Multiplexed I/O PSRAM

I/O
O Clock (for synchronous access)
O Address bus
I/O 16-bit multiplexed, bidirectional address/data bus
O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O Output enable
O Write enable
O Address valid PSRAM input (memory signal name: NADV)
I PSRAM wait input signal to the FSMC
RM0041 Rev 6
Function
Function
Function
RM0041