Capture/Compare Channels; Figure 112. Control Circuit In External Clock Mode 2; Figure 113. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2 to TIM5)

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal.

Counter clock = CK_INT =CK_PSC

Capture/compare channels

Each Capture/Compare channel (see

(including a shadow register), an input stage for capture (with digital filter, multiplexing and

prescaler) and an output stage (with comparator and output control).

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be

used as trigger input by the slave mode controller or as the capture command. It is

prescaled before the capture register (ICxPS).

Counter register

TI1F_Falling

(from channel 2)

113) is built around a capture/compare register

(from slave mode

TI2F_Falling

RM0041 Rev 6

To the slave mode controller

/1, /2, /4, /8

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