Wakeup Event Management; Functional Description - ST STM32F100 Series Reference Manual

RM0041
8.2.3

Wakeup event management

The STM32F100xx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
•
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
•
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to
8.2.4

Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a '1' to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a '1' in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a '1' to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set
An interrupt/event request can also be generated by software by writing a '1' in the software
interrupt/event register.
Hardware interrupt selection
To configure the 18 lines as interrupt sources, use the following procedure:
•
Configure the mask bits of the 18 Interrupt lines (EXTI_IMR)
• Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
•
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
External Interrupt Controller (EXTI) so that an interrupt coming from one of the 18 lines
can be correctly acknowledged.
Hardware event selection
To configure the 18 lines as event sources, use the following procedure:
•
Configure the mask bits of the 18 Event lines (EXTI_EMR)
•
Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)
®
-M3 System Control register. When the MCU
Section 8.2.4: Functional
RM0041 Rev 6
Interrupts and events
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