Tim Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32F100 Series Reference Manual

RM0041
14.4.7

TIM capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits in this register have different functions in input and output modes. For a given bit, OCxx
describes its function when the channel is configured in output mode, ICxx describes its
function when the channel is configured in input mode. Take care that the same bit can have
different meanings for the input stage and the output stage.
15 14 13
Res. OC2M[2:0]
IC2F[3:0]
rw rw rw
Output compare mode
Bit 15
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7
12 11 10 9
OC2PE OC2FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
Reserved, must be kept at reset value.
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register
Reserved, must be kept at reset value.
General-purpose timers (TIM12/13/14)
8 7 6
Res. OC1M[2:0]
IC1F[3:0]
rw rw rw
RM0041 Rev 6
5 4 3 2
OC1PE OC1FE
IC1PSC[1:0]
rw rw rw rw
1 0
CC1S[1:0]
rw rw
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