ST STM32F100 Series Reference Manual page 572

Inter-integrated circuit (I2C) interface
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
The following is the required sequence in master mode.
•
Program the peripheral input clock in I2C_CR2 register in order to generate correct
timings
•
Configure the clock control registers
•
Configure the rise time register
•
Program the I2C_CR1 register to enable the peripheral
•
Set the START bit in the I2C_CR1 register to generate a Start condition
The peripheral input clock frequency must be at least:
•
2 MHz in Sm mode
• 4 MHz in Fm mode
SCL master clock generation
The CCR bits are used to generate the high and low level of the SCL clock, starting from the
generation of the rising and falling edge (respectively). As a slave may stretch the SCL line,
the peripheral checks the SCL input from the bus at the end of the time programmed in
TRISE bits after rising edge generation.
•
If the SCL line is low, it means that a slave is stretching the bus, and the high level
counter stops until the SCL line is detected high. This allows to guarantee the minimum
HIGH period of the SCL clock parameter.
•
If the SCL line is high, the high level counter keeps on counting.
Indeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL
rising edge detection by the peripheral takes time even if no slave stretches the clock. This
loopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus
delay due to the noise filter present on the SCL input path, plus delay due to internal SCL
input synchronization with APB clock. The maximum time used by the feedback loop is
programmed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL
rising time.
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (MSL bit set) when the BUSY bit is cleared.
Note: In master mode, setting the START bit causes the interface to generate a ReStart condition
at the end of the current byte transfer.
Once the Start condition is sent:
•
The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see
572/709
Figure 237 and Figure 238
RM0041 Rev 6
Transfer sequencing EV5).
RM0041