Af Remap And Debug I/O Configuration Register (Afio_Mapr) - ST STM32F100 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
7.4.2

AF remap and debug I/O configuration register (AFIO_MAPR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Reserved
15 14 13 12
PD01_ TIM4_
REMAP REMAP
Reserved
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Bits 31:27 Reserved
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
Bits 23:17 Reserved.
Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
Bits 14:13
Bit 12 TIM4_REMAP: TIM4 remapping
Note: TIM4_ETR on PE0 is not re-mapped.
Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping
Note: TIM3_ETR on PE0 is not re-mapped.
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27 26 25
SWJ_CFG[2:0]
w w
11 10 9
TIM3_REMAP TIM2_REMAP
[1:0] [1:0]
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These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
®
access to the Cortex debug port. The default state after reset is SWJ ON without trace.
This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO
functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)
PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 48- and
64-pin packages (PD0 and PD1 are available on 100-pin packages, no need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
Reserved.
This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto
the GPIO ports.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to
4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
24 23 22 21
w
8 7 6 5
TIM1_REMAP USART3_
[1:0] REMAP[1:0]
rw rw rw rw
RM0041 Rev 6
20 19 18
Reserved
4 3 2
USART2_ USART1_
REMAP REMAP
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RM0041
17 16
TIM5CH4
_IREMAP
rw
1 0
I2C1_ SPI1_
REMAP REMAP
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