Figure 227. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0); Figure 228. Txe/Bsy In Slave Transmit-Only Mode (Bidimode=0 And Rxonly=0) In Case Of - ST STM32F100 Series Reference Manual

RM0041

Figure 227. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0)

Example in Master mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
software writes software waits
0xF1 into until TXE=1 and
SPI_DR writes 0xF2 into
SPI_DR

Figure 228. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of

Example in slave mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
software writes software waits
0xF1 into until TXE=1 and
SPI_DR writes 0xF2 into
SPI_DR
Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)
In this mode, the procedure is similar to the procedure in Transmit-only mode except that
the BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling
the SPI.
Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)
In this mode, the procedure can be reduced as described below (see
in case of continuous transfers
DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by hardware
software waits
until TXE=1 and
writes 0xF3 into
SPI_DR
continuous transfers
DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by hardware
software waits
until TXE=1 and
writes 0xF3 into
SPI_DR
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
software waits until TXE=1
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
software waits until TXE=1
RM0041 Rev 6
Serial peripheral interface (SPI)
DATA 3 = 0xF3
set by hardware
reset by hardware
software waits until BSY=0
DATA 3 = 0xF3
set by hardware
reset by hardware
software waits until BSY=0
Figure 229):
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