Table 105. Fsmc_Bwtrx Bit Fields; Figure 211. Mode C Read Accesses - ST STM32F100 Series Reference Manual

Flexible static memory controller (FSMC)
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its
content is don't care.
Mode C - NOR flash - OE toggling
510/709

Table 105. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x1
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses,
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET[3:0]
Minimum value for ADDSET is 0.

Figure 211. Mode C read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
HCLK cycles
RM0041 Rev 6
Value to set
Memory transaction
ADDSET
data driven
by memory
DATAST
HCLK cycles
RM0041
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