Counter Modes; Figure 159. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 160. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - ST STM32F100 Series Reference Manual

General-purpose timers (TIM15/16/17)

Figure 159. Counter timing diagram with prescaler division change from 1 to 2

Figure 160. Counter timing diagram with prescaler division change from 1 to 4

15.4.2

Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register plus one
(TIMx_RCR + 1). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
394/709
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
RM0041 Rev 6
F7 F8 F9 FA FB FC 00
0
0
0 1
0
F7 F8 F9 FA FB FC
0
0
0 1
0
RM0041
01 02 03
1
1
0 1 0 1 0 1
00 01
3
3
2 3 0 1 2 3