Usart Receiver Tolerance To Clock Deviation; Multiprocessor Communication; Table 129. Usart Receiver's Tolerance When Div Fraction Is 0; Table 130. Usart Receiver Tolerance When Div_Fraction Is Different From 0 - ST STM32F100 Series Reference Manual

RM0041
23.3.5

USART receiver tolerance to clock deviation

The USART asynchronous receiver works correctly only if the total clock system deviation is
smaller than the USART receiver's tolerance. The causes which contribute to the total
deviation are:
• DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
•
DQUANT: Error due to the baud rate quantization of the receiver
•
DREC: Deviation of the receiver's local oscillator
•
DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
DTRA + DQUANT + DREC + DTCL < USART receiver's tolerance
The USART receiver's tolerance to properly receive data is equal to the maximum tolerated
deviation and depends on the following choices:
•
10- or 11-bit character length defined by the M bit in the USART_CR1 register
•
oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
use of fractional baud rate or not
•
use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register
M bit
0
1

Table 130. USART receiver tolerance when DIV_Fraction is different from 0

M bit
0
1
Note: The figures specified in
the received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times
when M=1).
23.3.6

Multiprocessor communication

There is a possibility of performing multiprocessor communication with the USART (several
USARTs connected in a network). For instance one of the USARTs can be the master, its TX
output is connected to the RX input of the other USART. The others are slaves, their
Universal synchronous asynchronous receiver transmitter (USART)

Table 129. USART receiver's tolerance when DIV fraction is 0

OVER8 bit = 0
ONEBIT=0
3.75%
3.41%
OVER8 bit = 0
ONEBIT=0
3.33%
3.03%
Table 129 and
RM0041 Rev 6
ONEBIT=1
4.375%
3.97%
ONEBIT=1 ONEBIT=0
3.88%
3.53%
Table 130 may slightly differ in the special case when
OVER8 bit = 1
ONEBIT=0 ONEBIT=1
2.50% 3.75%
2.27% 3.41%
OVER8 bit = 1
ONEBIT=1
2%
1.82% 2.73%
3%
617/709
646