Table 102. Fsmc_Bwtrx Bit Fields; Figure 208. Mode2 And Mode B Read Accesses - ST STM32F100 Series Reference Manual

RM0041
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode 2/B - NOR flash

Table 102. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses,
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET[3:0]
Minimum value for ADDSET is 0.

Figure 208. Mode2 and mode B read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
HCLK cycles
RM0041 Rev 6
Flexible static memory controller (FSMC)
Value to set
Memory transaction
ADDSET
data driven
by memory
DATAST
HCLK cycles
ai15561
507/709
535