Table 140. Software Sequence To Respect When Receiving A Message; Figure 280. Example Of A Complete Message Reception - ST STM32F100 Series Reference Manual

High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC)
status register. The host CPU can either poll this register or enable interrupts in the
configuration status register to know whether a byte was received. If the RBTF bit is not
cleared by the time a new block is received, the newly received block is not acknowledged
to force the initiator to restart the message transmission, thus giving the host CPU a second
chance to retrieve all message bytes in time. Note that it is the responsibility of the software
driver to ignore messages where the number of operands is less than the number specified
for the opcode.
The figure below shows an example of a complete message reception.
CEC lin e
Inter rupt
RX buf fer
The software has to respect the sequence described in the table below.
Poll RBTF or wait until an interrupt occurs
A header is received (RTBF and RSOM are
set)
Read header from RX buffer
Acknowledge received byte by writing 0x00
Poll RBTF or wait until an interrupt occurs
An opcode is received (RBTF is set)
Read opcode from RX buffer
Acknowledge received byte by writing 0x00
Poll RBTF or wait until an interrupt occurs
An operand is received (RBTF is set)
Read Operand1 from RX buffer
Acknowledge received byte by writing 0x00
Poll RBTF or wait until an interrupt occurs
An operand is received, which is the last
data byte (RBTF and REOM are set)
Read Operand2 from RX buffer
Acknowledge received byte by writing 0x00
1. Two different values may be read from the control and status register since a message may have queued
for transmission but arbitration has been lost.
658/709

Figure 280. Example of a complete message reception

Start
Header
bit

Table 140. Software sequence to respect when receiving a message

Software sequences
Opcode Operand1
Header Opcode
CEC_CSR register
R/W access
Read 0x00
Read 0x90 or 0x91
-
Write 0x00
Read 0x00
Read 0x80 or 0x81
-
Write 0x00
Read 0x00
Read 0x80 or 0x81
-
Write 0x00
Read 0x00
Read 0xA0 or 0xA1
-
Write 0x00
RM0041 Rev 6
Operand2
(with EOM=1,
last data byte)
Operand1 Operand2
Status bits
RTBF RERR REOM
bit 7 bit 6 bit 5
0 0 0
(1)
1 0 0
1 0 0
0 0 0
0 0 0
1 0 0
1 0 0
0 0 0
0 0 0
1 0 0
1 0 0
0 0 0
0 0 0
1 0 1
1 0 1
0 0 0
ai17326
RSOM
bit 4
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0