Figure 40. Advanced-Control Timer Block Diagram - ST STM32F100 Series Reference Manual

Advanced-control timer (TIM1)
CK_TIM18 from RCC
ETR
Polarity selection,
Edge detector and Prescaler
ITR0
ITR1
ITR2
ITR3
TI1
Input filter &
Edge detector
TI2
Input filter &
Edge detector
TI3
Input filter &
Edge detector
TI4
Input filter &
Edge detector
BRK
Polarity selection
Clock failure event from clock controller
CSS (Clock Security System)
Interrupt & DMA output
Event
214/709

Figure 40. Advanced-control timer block diagram

Internal clock (CK_INT)
ETRF
ETRP
Input filter
TGI
TRGI
TRC
TIF_ED
TI1FP1
TI2FP2
CK_PSC
TI1FP1
IC1
TI1FP2
TRC
TI2FP1
IC2
TI2FP2
TRC
TI3FP3
IC3
TI3FP4
TRC
TI4FP3
IC4
TI4FP4
TRC
Trigger
controller
Slave mode
controller
Reset,
Enable,
Up/Down,
Count
Encoder
interface
AutoReload
U
Register
CK_CNT
PSC CNT
(prescaler) (counter)
CC1I
IC1PS
Capture/Compare
Prescaler
1 Register
U U
CC2I
IC2PS
Capture/Compare
Prescaler
2 Register
U
CC3I
IC3PS
Capture/Compare
Prescaler
3 Register
U
CC4I
IC4PS
Capture/Compare
Prescaler
4 Register
U
BI
RM0041 Rev 6
TRGO
To other timers
To DAC and ADC
REP Register
Repetition counter
DTG[7:0] registers
CC1I
OC1REF
Output
DTG
control
CC2I
OC2REF
Output
DTG
control
CC3I
OC3REF
Output
DTG
control
CC4I
OC4REF
Output
control
RM0041
UI
U
OC2N
OC3
OC4
MS39906V3