Tim15 Slave Mode Control Register (Tim15_Smcr) - ST STM32F100 Series Reference Manual

General-purpose timers (TIM15/16/17)
Bit 2 CCUS: Capture/compare control update selection
Note: This bit acts only on channels that have a complementary output.
Bit 1
Bit 0 CCPC: Capture/compare preloaded control
Note: This bit acts only on channels that have a complementary output.
15.5.3

TIM15 slave mode control register (TIM15_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13
Bits 15:8
Bit 7 MSM: Master/slave mode
418/709
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Reserved, must be kept at reset value.
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
12 11 10 9
Reserved
Reserved, must be kept at reset value.
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
8 7 6
MSM TS[2:0]
rw rw
RM0041 Rev 6
5 4 3 2
Res.
rw rw rw
RM0041
1 0
SMS[2:0]
rw rw