Table 106. Fsmc_Bcrx Bit Fields; Figure 212. Mode C Write Accesses - ST STM32F100 Series Reference Manual

RM0041
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Bit No.
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2

Figure 212. Mode C write accesses

A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
HCLK cycles

Table 106. FSMC_BCRx bit fields

Bit name
Reserved
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP[0:1]
RM0041 Rev 6
Flexible static memory controller (FSMC)
Memory transaction
data driven by FSMC
ADDSET
0x000
0x0 (no effect on asynchronous mode)
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
at 0.
0x1
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
0x2 (NOR flash memory)
1HCLK
(DATAST + 1)
HCLK cycles
Value to set
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