ST STM32F100 Series Reference Manual page 705

RM0041
Date
10-Jun-2016
Table 161. Document revision history (continued)
Revision
Updated:
– Introduction
– Section 2.1: System
– Section 25.6.1: MCU device ID
– Section 4.4.2: Power control/status register
– Section 6.1.2: Power
– Section 7.2.3: Port input data register (GPIOx_IDR) (x=A..G)
Section 7.2.4: Port output data register (GPIOx_ODR) (x=A..G)
– Section 8.2: External interrupt/event controller
Software interrupt event register (EXTI_SWIER)
Pending register
– Section 10.11.7: ADC watchdog high threshold register (ADC_HTR)
Section 10.11.8: ADC watchdog low threshold register
Renumbered former
Updated:
– Section 12.3.1: Time-base
Section 12.3.6: Input capture
outputs and dead-time
signal on an external
Section 12.3.18: Interfacing with Hall
slave mode control register
register 2 (TIMx_CR2),
5
register 1 (TIMx_CCMR1),
continued
(TIMx_ARR),
mode, Section 13.3.11: Clearing the OCxREF signal on an external
event, Section 13.3.12: Encoder interface
synchronization,
Section 13.4.3: TIMx slave mode control register
Section 13.4.7: TIMx capture/compare mode register 1
Section 14.3.1: Time-base
Section 14.3.9: PWM
register 1 (TIMx_CCMR1),
mode register 1
Section 15.3: TIM16 and TIM17 main
base unit,
counter, Section 15.4.6: Input capture
mode, Section 15.4.11: Complementary outputs and dead-time
insertion, Section 15.5.3: TIM15 slave mode control register
(TIM15_SMCR),
1 (TIM15_CCMR1),
(TIM15_ARR),
(TIM15_BDTR),
register 1 (TIMx_CCMR1),
register (TIMx_ARR)
dead-time register
Updated:
– Section 19.4: How to program the watchdog
RM0041 Rev 6
Changes
architecture, Section 2.3: Memory map
code.
reset, Section 6.2.8: RTC clock
(EXTI_PR).
Section 14.3 into
unit, Section 12.3.2: Counter
mode,
insertion, Section 12.3.13: Clearing the OCxREF
event, Section 12.3.16: Encoder interface
(TIMx_SMCR),
Section 12.4.7: TIM1 capture/compare mode
Section 12.4.12: TIM1 auto-reload register
Section 13.3.5: Input capture
Section 13.4.2: TIMx control register 2
unit, Section 14.3.5: Input capture
mode, Section 14.4.7: TIM capture/compare mode
Section 14.5.5: TIM13/14 capture/compare
(TIMx_CCMR1), Section 15.2: TIM15 main
Section 15.4.2: Counter
Section 15.5.7: TIM15 capture/compare mode register
Section 15.5.11: TIM15 auto-reload register
Section 15.5.15: TIM15 break and dead-time register
Section 15.6.6: TIM16&TIM17 capture/compare mode
Section 15.6.10: TIM16&TIM17 auto-reload
and Section 15.6.13: TIM16&TIM17 break and
(TIMx_BDTR).
Revision history
(PWR_CSR),
(EXTI), Section 8.3.5:
and Section 8.3.6:
(ADC_LTR).
Section 14.2.2.
modes,
Section 12.3.11: Complementary
sensors, Section 12.4.3: TIM1
Section 12.4.2: TIM1 control
mode, Section 13.3.9: PWM
mode, Section 13.3.15: Timer
(TIMx_CR2),
(TIMx_SMCR),
(TIMx_CCMR1),
features, Section 15.4.1: Time-
modes, Section 15.4.3: Repetition
mode, Section 15.4.10: PWM
timeout.
and
and
mode,
mode,
features,
705/709
706