Digital-to-analog converter (DAC)
XOR
X
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a '1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
Figure 37. DAC conversion (SW trigger enabled) with LFSR wave generation
APB1_CLK
DHR
DOR
SWTRIG
Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
11.3.9
Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to "10". The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
196/709
Figure 36. DAC LFSR register calculation algorithm
12
11
10
9
0x00
6
X
8
7
6
5
12
NOR
0xAAA
RM0041 Rev 6
4
X
X
4
3
2
1
0xD55
RM0041
0
X
0
ai14713c
ai14714b
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