Figure 125. Control Circuit In Gated Mode - ST STM32F100 Series Reference Manual

General-purpose timers (TIM2 to TIM5)
Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, no need of any filter, IC1F=0000 kept). The capture prescaler is not
used for triggering, so the user does not need to configure it. The CC1S bits select the
input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and
CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).
•
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter does not start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Counter clock = CK_CNT = CK_PSC
Note: The configuration "CCxP=CCxNP=1" (detection of both rising and falling edges) does not
have any effect in gated mode because gated mode acts on a level and not on an edge.
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
•
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, no need of any filter, IC2F=0000 kept). The capture prescaler is not
used for triggering, so the user does not need to configure it. CC2S bits are selecting
the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and
CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only).
• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
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Figure 125. Control circuit in gated mode

TI1
CNT_EN
Counter register
30 31
TIF
RM0041 Rev 6
32 33 34
Write TIF=0
RM0041
35 36 37 38
MS40512V1