Ahb Peripheral Clock Enable Register (Rcc_Ahbenr) - ST STM32F100 Series Reference Manual

Reset and clock control (RCC)
Bit 11 WWDGRST: Window watchdog reset
Bits 10:9
Bit 8 TIM14RST: Timer 14 reset
Bit 7 TIM13RST: Timer 13 reset
Bit 6 TIM12RST: Timer 12 reset
Bit 5 TIM7RST: Timer 7 reset
Bit 4 TIM6RST: Timer 6 reset
Bit 3 TIM5RST: Timer 5 reset
Bit 2 TIM4RST: Timer 4 reset
Bit 1 TIM3RST: Timer 3 reset
Bit 0 TIM2RST: Timer 2 reset
6.3.6

AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
90/709
Set and cleared by software.
0: No effect
1: Reset window watchdog
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset timer 14
Set and cleared by software.
0: No effect
1: Reset timer 13
Set and cleared by software.
0: No effect
1: Reset timer 12
Set and cleared by software.
0: No effect
1: Reset timer 7
Set and cleared by software.
0: No effect
1: Reset timer 6
Set and cleared by software.
0: No effect
1: Reset timer 5
Set and cleared by software.
0: No effect
1: Reset timer 4
Set and cleared by software.
0: No effect
1: Reset timer 3
Set and cleared by software.
0: No effect
1: Reset timer 2
RM0041 Rev 6
RM0041