Adc Control Register 1 (Adc_Cr1) - ST STM32F100 Series Reference Manual

Analog-to-digital converter (ADC)
10.11.2

ADC control register 1 (ADC_CR1)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
JDISCE
DISCNUM[2:0]
N
rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set/reset by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set/reset by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:16 Reserved, must be kept at reset value.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
.......
111: 8 channels
Bit 12 JDISCEN: Discontinuous mode on injected channels
This bit set and cleared by software to enable/disable discontinuous mode on injected group
channels
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Bit 11 DISCEN: Discontinuous mode on regular channels
This bit set and cleared by software to enable/disable Discontinuous mode on regular
channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic Injected Group conversion
This bit set and cleared by software to enable/disable automatic injected group conversion
after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
176/709
27 26 25
Reserved
11 10 9
DISC AWD
JAUTO
EN SGL
rw rw rw
24 23 22
AWDE JAWDE
N N
rw rw
8 7 6
JEOC
SCAN AWDIE EOCIE
IE
rw rw rw
RM0041 Rev 6
21 20 19 18
Reserved
5 4 3 2
AWDCH[4:0]
rw rw rw rw
RM0041
17 16
1 0
rw rw