Figure 229. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1) - ST STM32F100 Series Reference Manual

Serial peripheral interface (SPI)
1. Set the RXONLY bit in the SPI_CR1 register.
2. Enable the SPI by setting the SPE bit to 1:
a)
b)
3. Wait until RXNE=1 and read the SPI_DR register to get the received data (this clears
the RXNE bit). Repeat this operation for each data item to be received.
This procedure can also be implemented using dedicated interrupt subroutines launched at
each rising edge of the RXNE flag.
Note: If it is required to disable the SPI after the last transfer, follow the recommendation
described in

Figure 229. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1)

Example with CPOL=1, CPHA=1, RXONLY=1
SCK
MISO/MOSI (in)
RXNE flag
Rx buffer
(read from SPI_DR)
Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)
In this mode, the procedure is similar to the Receive-only mode procedure except that the
BIDIMODE bit has to be set and the BIDIOE bit cleared in the SPI_CR2 register before
enabling the SPI.
Continuous and discontinuous transfers
When transmitting data in master mode, if the software is fast enough to detect each rising
edge of TXE (or TXE interrupt) and to immediately write to the SPI_DR register before the
ongoing data transfer is complete, the communication is said to be continuous. In this case,
there is no discontinuity in the generation of the SPI clock between each data item and the
BSY bit is never cleared between each data transfer.
On the contrary, if the software is not fast enough, this can lead to some discontinuities in
the communication. In this case, the BSY bit is cleared between each data transmission
(see Figure
In Master receive-only mode (RXONLY=1), the communication is always continuous and
the BSY flag is always read at 1.
550/709
In master mode, this immediately activates the generation of the SCK clock, and
data are serially received until the SPI is disabled (SPE=0).
In slave mode, data are received when the SPI master device drives NSS low and
generates the SCK clock.
Section 21.3.8.
in case of continuous transfers
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits until RXNE=1
and reads 0xA1 from SPI_DR
230).
DATA 2 = 0xA2
cleared by software
0xA1
software waits until RXNE=1
and reads 0xA2 from SPI_DR
RM0041 Rev 6
DATA 3 = 0xA3
0xA2
software waits until RXNE=1
and reads 0xA3 from SPI_DR
RM0041
0xA3
ai17347