Spi Status Register (Spi_Sr) - ST STM32F410 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
Bit 2 SSOE: SS output enable
Note: This bit is not used in I
Bit 1 TXDMAEN: Tx buffer DMA enable
Bit 0 RXDMAEN: Rx buffer DMA enable
25.7.3

SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13
Res. Res. Res. Res.
Bits 15:9 Reserved. Forced to 0 by hardware.
Bit 8 FRE: Frame Error
Bit 7 BSY: Busy flag
Note: BSY flag must be used with caution: refer to
Bit 6 OVR: Overrun flag
724/771
0: SS output is disabled in master mode and the cell can work in multimaster configuration
1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work
in a multimaster environment.
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
12 11 10 9
Res. Res. Res.
0: No frame error
1: Frame error occurred.
This bit is set by hardware and cleared by software when the SPI_SR register is read.
This bit is used in SPI TI mode or in I2S mode whatever the audio protocol selected. It
detects a change on NSS or WS line which takes place in slave mode at a non expected
time, informing about a desynchronization between the external master device and the
slave.
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Section 25.3.10: Procedure for disabling the
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
error flags for the software sequence.
2
S mode and SPI TI mode.
8 7 6
FRE BSY OVR MODF
r r r
Section 25.3.12: SPI status flags
SPI.
RM0401 Rev 3
5 4 3 2
CRC
UDR CHSIDE
ERR
r rc_w0 r r
Section 25.3.13: SPI
RM0401
1 0
TXE RXNE
r r
and