Spi Status Register (Spi_Sr) - ST STM32F207 Series Reference Manual

Serial peripheral interface (SPI)
Bit 1 TXDMAEN: Tx buffer DMA enable
Bit 0 RXDMAEN: Rx buffer DMA enable
25.5.3

SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13
Reserved
Bits 15:9 Reserved. Forced to 0 by hardware.
Bit 8 TIFRFE: TI frame format error
Bit 7 BSY: Busy flag
Note: BSY flag must be used with caution: refer to
Bit 6 OVR: Overrun flag
Bit 5 MODF: Mode fault
Note: This bit is not used in I
Bit 4 CRCERR: CRC error flag
Note: This bit is not used in I
728/1381
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
12 11 10 9
0: No frame format error
1: A frame format error occurred
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
Error flags
for the software sequence.
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
Error flags
for the software sequence.
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
8 7 6
TIFRF
BSY OVR MODF
E
r r r
Section 25.3.7
2
S mode
2
S mode.
RM0033 Rev 9
5 4 3 2
CRC
UDR CHSIDE
ERR
r rc_w0 r r
and Section
Section 25.4.7:
Section 25.4.7:
RM0033
1 0
TXE RXNE
r r
25.3.8.