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6.3.4 Bus Control Signal Timing
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8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper address bus (D
pin is always high. Wait states can be inserted.
ø
Address bus
CS
n
AS
RD
Read
D
to D
15
access
D to D
7
HWR
LWR
Write
access
D
to D
15
D to D
7
Note: n = 7 to 0
Figure 6-4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
T
1
8
0
High
8
0
) is used to access these areas. The LWR
to D
15
8
Bus cycle
T
2
External address in area n
Valid
Undetermined data
125
T
3
Valid
Invalid
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