Table of Contents
Advertisement
ø
Upper
address bus
Lower
address bus
CSn
AS
RD
Data bus
Note: n = 1 or 0
4.6.3
Wait Control
As with the basic bus interface, either (1) program wait insertion or (2) pin wait insertion using the
WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section
4.4.5, Wait Control.
Wait states cannot be inserted in a burst cycle.
4.6.4
Write Access
When a write access to burst ROM interface space is executed, burst access is interrupted at that
point and the write access is executed in line with the basic bus interface settings.
Write accesses are not performed in burst mode even though burst ROM space is designated.
164
T 1
Figure 4.43 Example of Burst ROM Access Timing (2)
(ASTn = 0, 1-State Burst Cycle)
Full access
Burst access
T 2
T 1
T 1
Advertisement
Table of Contents
