Register And Pin Input Timing; Register Write Timing; Figure 6.22 Astcr Write Timing; Figure 6.23 Ddr Write Timing - Hitachi H8/3062 Hardware Manual

6.7

Register and Pin Input Timing

6.7.1

Register Write Timing

ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
φ
Address bus
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T
the DDR write cycle. Figure 6.23 shows the timing when the CS
input to CS
output.
1
φ
Address bus
CS
BRCR Write Timing: Data written to BRCR to switch between A
generic input or output takes effect starting from the T
6.24 shows the timing when a pin is changed from generic input to A
162
T T T
1 2 3
3-state access to area 0

Figure 6.22 ASTCR Write Timing

1
High-impedance

Figure 6.23 DDR Write Timing

T T T
1 2 3
ASTCR address
2-state access to area 0
1
T T
1 2
P8DDR address
state of the BRCR write cycle. Figure
3
T T
1 2
pin is changed from generic
T
3
, A , A , or A output and
23 22 21 20
, A , A , or A
23 22 21 20
state of
3
output.