Usage Notes; Register Write Timing - Hitachi H8/3032 Series Hardware Manual

6.4 Usage Notes

6.4.1 Register Write Timing

ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from
the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 0 changes
area 0 from three-state access to two-state access.
ø
Address
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T T T T
1 2 3 1
3-state access to area 0
Figure 6-11 ASTCR Write Timing
T T T
2 3 1
ASTCR address
2-state access
to area 0
118
T
2