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34. Revision History
Revision 1.1
March, 2018
• Removed PLFRCO and associated details throughout document.
•
9.3.3 Power-On Reset
(POR): Clarification of Power-On Reset supply connection (AVDD) and threshold (1.2V).
• Added information about analog peripheral power connections and VDDX_ANA supply rail throughout document.
• Added information about IOVDD and AVDD restrictions on analog input signals throughout document.
•
10.3.9.1 EM01 Voltage
Scaling: Clarification of reset effects on voltage scaling operations in progress.
•
10.3.12 Voltage Monitor
(VMON): Added note about VMON hystereis and riding/falling thresholds.
•
11.3.2.4 HFXO
Configuration: Clarified steady state timeout and state transition to ready.
•
11.3.2.5 LFXO
Configuration: Added recommendations for GAIN setting.
•
15.3.1.3 Configurable PRS
•
15.3.2
Producers: Added more detail about GPIO producer source.
•
15.3.5 DMA Request on
PRS: Fixed incorrect bit / register names and clarified signals for DMA are PRSRQE0 and PRSREQ1.
•
26.3.17 ADC Programming
Revision 1.0
October, 2017
• Remove "Confidential" watermark.
Revision 0.1
September 17th, 2017
Initial release.
silabs.com | Building a more connected world.
Logic: Clarified ANDNEXT and ORPREV behavior for first and last PRS channels.
Model: Added note about changing to ASYNC clock mode with KEEPADCWARM.
Reference Manual
Revision History
Rev. 1.1 | 1136
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