Input Capture Timing - Hitachi H8/3672 Series Hardware Manual

Figure 11-16 shows the output compare timing.
φ
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
FTIOA to FTIOD
11.5.3

Input Capture Timing

Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 11-17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
ø
Input capture
input
Input capture
signal
TCNT
GRA to GRD
N
N
Figure 11-16 Output Compare Output Timing
N–1
Figure 11-17 Input Capture Input Signal Timing
N+1
N N+1
N
Rev. 1.0, 03/01, page 143 of 280
N+2