Input Capture Signal Timing - Hitachi H8/3062 Hardware Manual

Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this
operation.
φ
Compare match signal
8TCNT N H'00
Figure 9.11 Timing of Clear by Compare Match
Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when input capture B occurs. Figure 9.12 shows the timing of this
operation.
φ
Input capture input
Input capture signal
8TCNT
N H '00
Figure 9.12 Timing of Clear by Input Capture
9.4.3

Input Capture Signal Timing

Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR.
Figure 9.13 shows the timing when the rising edge is selected.
The pulse width of the input capture input signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected.
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