Dma Control Register (Dmacr) - Hitachi H8S/2338 Series Hardware Manual

Repeat Mode
Transfer Number Storage (ETCRH)
Bit : 15
Initial value :
R/W : R/W
Transfer Counter (ETCRL)
Bit :
Initial value :
R/W : R/W
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and
transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is
performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this
point, MAR is automatically restored to the value it had when the count was started. The DTE bit
in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is
cleared by the user.
ETCR is not initialized by a reset or in standby mode.
5.2.4

DMA Control Register (DMACR)

Bit :
DTSZ
Initial value :
R/W : R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
122
14 13
* *
R/W R/W
7 6
* *
R/W R/W
7 6
DTID5 RPE
0 0
R/W R/W
12 11
* *
R/W R/W
5 4
* *
R/W R/W
5 4
DTDIR DTF3
0 0
R/W R/W
10
* *
R/W R/W
3 2
* *
R/W R/W
3 2
DTF2 DTF1
0 0
R/W R/W
9 8
* *
R/W
1 0
* *
R/W
*: Undefined
1 0
DTF0
0 0
R/W