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6.5
Idle Cycle
6.5.1
Operation
When the H8/3062 Series chip accesses external space, it can insert a 1-state idle cycle (T
between bus cycles in the following cases: when read accesses between different areas occur
consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle
cycle it is possible, for example, to avoid data collisions between ROM, which has a long output
floating time, and high-speed memory, I/O interfaces, and so on.
The initial value of the ICIS1 and ICIS0 bits in BCR is 1, so that idle cycle insertion is performed
in the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is
inserted, and a data collision is prevented.
φ
Address bus
RD
Data bus
(a) Idle cycle not inserted
Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.19 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
154
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
1
2
Long buffer-off time
φ
Address bus
RD
Data bus
Data collision
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
i
1
(b) Idle cycle inserted
)
i
T
2
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