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3.4 Operating Mode Descriptions
3.4.1 Mode 1
1-Mbyte address space can be accessed including the on-chip ROM addresses. Port 3 pins
function as data I/O pins D
The address bus width can be selected by setting DDR of ports 1, 2, and 5.
3.4.2 Mode 2
16-Mbyte address space can be accessed including the on-chip ROM addresses. Port 3 pins
function as data I/O pins D
pins A
to A
. The address bus width can be selected by setting DDR of ports 1, 2, and 5, and
23
0
ADRCR of port A.
In this mode, address pin A
3.4.3 Mode 3
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. External addresses cannot be accessed.
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1, 2, 3, 5, 6 and A vary depending on the operating mode. Table 3-3
indicates their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port
Mode 1
Port 1
P1
to P1
7
0*1
Port 2
P2
to P2
7
0*1
Port 3
D
to D
7
0
Port 5
P5
to P5
3
0*1
:5
5'
$6
Port 6
,
,
Port A
PA
to PA
7
4
Notes: 1. Initial state. These pins function as an address bus by setting the corresponding DDR
bit to 1.
2. The functions of these pins vary depending on the settings in the wait state controller
enable register (WCER), wait control register (WCR), and port data direction register.
A
3. Initial state.
A
to A
outputs by clearing bits 7 to 5 of ADRCR to 0.
23
21
to D
and port 1, 2, and 5 pins function as address pins A
7
0
to D
and port 1, 2, 5, and A (PA
7
0
always functions as an address output.
20
Mode 2
P1
to P1
7
P2
to P2
7
D
to D
7
0
P5
to P5
3
:$,7
:5
5'
, P6
/
,
0
*2
PA
to PA
6
always functions as an address output.
20
to PA
) pins function as address
7
4
Mode 3
P1
0*1
7
P2
0*1
7
P3
7
P5
0*1
3
$6
:$,7
P6
,
, P6
/
5
0
*2
A
PA
7
4,
20*3
PA
to PA
6
to A
.
19
0
to P1
0
to P2
0
to P3
0
to P5
0
to P6
, P6
3
0
to PA
4
are switched to
4
57
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