Instructions That Disable Interrupts; When Interrupts Are Disabled; Figure 5.6 Conflict Between Interrupt Generation And Disabling - Hitachi H8S/2628 Hardware Manual

φ
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal

Figure 5.6 Conflict between Interrupt Generation and Disabling

5.7.2

Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3

When Interrupts Are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
TIER_0 write cycle by CPU
TIER_0 address
TCIVexception handling
Rev. 1.0, 09/02, page 83 of 568